A) Field of the Invention
The present invention relates to a semiconductor device for reading an electric signal of each of a plurality of pixels disposed on a semiconductor substrate to a signal read line via transistors, the electric signal being photoelectrically converted by a photodiode of the pixel.
B) Description of the Related Art
A solid state imaging device (image sensor) manufactured based upon complimentary MOS (CMOS) processes generally uses an active pixel sensor (APS) in whose pixel is constituted of: a photodiode for conducting photoelectric conversion; a reset transistor for initializing a voltage to be applied to the photodiode; a source follower transistor for converting signal charges of the photodiode into a voltage signal and outputting it; and a select transistor for selecting the pixel to read the voltage signal.
FIG. 13A is a plan view of one pixel of a conventional four-transistor solid state imaging device. Active regions 500 are defined in a silicon substrate. The active region 500 is constituted of: a rectangular area 500A; a projecting area 500B projecting right from the upper right side of the rectangular area 500A as viewed in FIG. 13A; a vertical area 500C extending from the front portion of the projecting area 500B toward the lower portion in FIG. 13A; and a horizontal area 500D extending from the lower edge of the vertical area 500C toward the left as viewed in FIG. 13A.
A photodiode PD is disposed in the rectangular area 500A. The gate electrode of a transfer transistor TTR crosses the vertical area 500C. In the area lower than this cross area, the gate electrode of a reset transistor TRS crosses the vertical area 500C. The gate electrode of a source follower transistor TSF crosses the horizontal area 500D. On the left side of this cross area, the gate electrode of a select transistor TSL crosses the horizontal area 500D.
A via hole HFD interconnecting an impurity diffusion region and the gate electrode of the source follower transistor TSF is disposed between the gate electrodes of the transfer transistor TTR and reset transistor TRS. A via hole HRS interconnecting an impurity diffusion region and a reset voltage supply line formed in the upper layer is disposed between the gate electrodes of the reset transistor TRS and source follower transistor TSF. A via hole HSIG interconnecting the source region of the select transistor and a signal read line formed in the upper layer is disposed on the left side of the gate electrode of the select transistor TSL.
In manufacturing a CMOS solid state imaging device, processes similar to those of manufacturing general logic circuit elements are basically used. Processes (logic processes) of manufacturing logic circuit elements in the generation of 0.35 μm rules or later fill tungsten in such via holes. The gate electrode of each transistor and the via holes are disposed by taking a position misalignment into consideration.
FIG. 13B is a plan view of one pixel of a conventional three-transistor solid state imaging device. A transistor corresponding to the transfer transistor TTR of the four-transistor solid state imaging device shown in FIG. 13A is omitted. The gate electrode of the source follower transistor TSF crosses the vertical area 500C of the active region 500 near at its lower edge. The gate electrode of the select transistor TSL branches from a select signal line SEL formed in the same wiring layer as that of the gate electrode. Instead of the via hole HFD, a via hole HPD is disposed for interconnecting the anode of the photodiode PD and the gate electrode of the source follower transistor TSF. The other fundamental structures are same as those of the four-transistor CMOS imaging device shown in FIG. 13A.
One pixel of a conventional general CMOS solid state imaging device has a square shape with four equal sides of, e.g., 5.6 μm. Since a photodiode PD and three or four transistors are disposed in one pixel, the area occupied by other than the photodiode PD becomes large and the ratio occupied by the photodiode PD in one pixel becomes small.
If the area of one pixel is made small in order to improve a pixel density, light convergence of a micro lens becomes difficult. Since the area occupied by the photodiode becomes small, incident light is reduced and the sensitivity is lowered.
Signal lines for supplying electric signals to the gates of the four transistors of a four transistor solid state imaging device are disposed in upper layers. Since the upper level wiring lines cannot run in the region where the photodiode PD is disposed, the wiring layout is not easy.
If the aspect ratio of a pixel can be freely selected, the ratio of an area occupied by a photodiode can be raised relatively easily. Generally, the vertical and horizontal pitches of pixels of a solid state are equal and each pixel has a square shape. The aspect ratio of a pixel cannot be therefore freely selected.
A significant issue of a CMOS solid state imaging device is concerned about reduction in junction leak current. A pixel having a large junction leak current becomes a white dot which degrades the image quality. As shown in FIG. 13B, in the case of a three-transistor solid imaging device among others, the plug in the via hole HFD contacts one of electrodes (n-type impurity diffusion regions) of a photodiode PD. This contact of the plug is one factor of increasing junction leak current.